- Architosh Staff (email@example.com)
- 1 Dec 2001 [Updated: 2
latest PowerPC RoadMap - G5 Info
[Editor's Note: See further notes and clarifications
in red below.]
On November 30, 2001, (the same Friday we
published a report on the G5 Power Macs and future Apple technologies)
Motorola published the latest PowerPC RoadMap, entitled "Motorola
Processor Strategy: Based upon the PowerPC Architecture".
G5 Architecture RoadMap Summary
The PowerPC MPC85xx family of processors are fifth-generation RISC-chip
microprocessors from Motorola featuring:
- Extensible Architecture
- New Pipeline
- New bus topology/RapidIO Interconnect Architecture
- 32 & 64-bit products with backward compatibility
- Symmetric Processing Capabilities
- 0.13 micron process with SOI initial G5 product
- 800MHz to 2GHz +
It is interesting that the RoadMap document doesn't make mention
of AltiVec. You can download the RoadMap (dated 11/30/2001) here
Apple's new G5 Power Macs
As we discussed in
our report yesterday, reliable sources have told us that G5
Power Macs in sealed and generic enclosures have been in the hands
of product testers for approximately four months now. It is unclear
to us if Apple and Motorola have had adequate time (usually six
months, and sometimes more) for complete product testing of new
While there is significant pressure by Apple's users for them to
offer much faster computers with next-generation microprocessors,
Steve Jobs & Co. may be concerned about repeating history with
the G5 product launch. For those that remember the G4 product launch,
Apple introduced the new G4's at Seybold in the Fall only to fail
to deliver the fastest introduced machines until many months later.
It is also unclear if the Motorola MPC8540 [or
similar cousin chip] is the G5 chip Apple will deliver in
its next generation Power Macintosh. Technical data on Moto's Web
site says this chip has a clock range of only 600 MHz - 1 GHz. Regardless
of the megahertz listings, this chip has impressive new technologies,
most importantly its RapidIO Interconnect Architecture.
New Technologies in the MPC8540
The MPC8540 is the first chip by Moto based on the eBook Architecture
and there is an excellent Microprocessor Forum presentation PDF
document on this page to review in detail. The MPC8540's Memory
Controller supports DDR SDRAM (20Gb/s) at 333MHz, with support for
4 GB's of RAM (that's for each G5 chip).
RapidIO Interconnect technology is a new high-speed chip-to-chip
interconnect technology. There is an excellent graphic in the above
referenced PDF document. RapidIO appears to be able to connect two
MPC8540 processors to each other at 500Mhz with 16Gb/s bandwidth.
Apple may be using the RapidIO technology for connecting to a new
graphics processor or graphics memory technology. This is high art
speculation at best.
Quad or More G5 Power Macs?
In reviewing the Moto info there is one interesting page, entitled
"MPC8540 Applications", which graphically shows four MPC8540
processors (each with their own memory (1-4 GB range) connected
by RapidIO and a RapidIO Switch. In this diagram RapidIO Interconnect
is a pervasive "chip-to-chip via controller/switch" interconnect
technology. Looks very interesting to those who are excited about
the possibility that Apple may introduce Quad G5 Power Macs.
Several readers have mentioned that the MPC8540
microprocessor cannot be the G5 chip in the new Power Macs as it
is for embedded host applications. We were initially unclear about
the possibility that this chip could be used outside this application.
Also, the question about AltiVec gone missing on the PowerPC Road
Map for G5 processors should not be taken as a sign that AltiVec
will not be in the next G5 Power Macs. Several readers and sources
have mentioned to us that Apple has built (speed) dependencies on
AltiVec throughout its OS and software line.
It is now our firmer belief that the G5 used
in the next Power Mac is similar to the MPC8540 but contains AltiVec
processing units. And while the MPC8540 contains a 333MHz memory
bus the G5 used in Apple's next Macs will have a 400MHz memory bus.]
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